1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a plurality of boosting voltage generators, each of which independently supplies a boosted voltage to each of a plurality of memory cell arrays.
2. Description of the Related Art
The threshold voltage of a transistor has a direct effect on the function and characteristic of the circuits which employ it. When an input voltage is transmitted to an arbitrary terminal through a transistor, the input voltage drops by the threshold voltage of the transistor. Hence, a voltage difference between the input voltage and output voltage is caused by the threshold voltage of the transistor. Therefore, when directly outputting an applied voltage to a desired terminal, the voltage supplied to the gate electrode of the transistor should be high in order to reduce the voltage drop caused by the threshold voltage of the transistor.
Semiconductor memory devices use a boosting voltage (hereinafter, referred to as Vpp) generator which generates a boosted voltage higher than a power supply voltage Vcc and thus has a voltage level of Vcc+.alpha.. A representative example of such a boosted voltage in the semiconductor memory device is a word line voltage, which is supplied to the gate of a memory cell transistor and allows reading and storage of information to and from a cell capacitor, respectively. With a boosted word line voltage, the voltage drop caused due to the threshold voltage of the cell transistor is compensated for and the information can be transmitted without any change due to threshold voltage losses of the memory cell transistor.
Dynamic random access memory (DRAM) devices perform a refresh operation during set periods to maintain the information stored in the cell capacitor. This refresh operation needs to be performed on all the memory cell arrays included in the DRAM. Thus, the larger the memory capacity of the semiconductor memory device, the greater the number of simultaneously activated word lines.
FIG. 1 is a circuit diagram showing a configuration of a single V.sub.pp generator in a conventional semiconductor memory device. Memory cell arrays MCA1-MCA8 respectively include a plurality of cell capacitors and cell transistors. Eight or more memory cell arrays can be provided. Word line drivers WD1-WD8 supply the Vpp voltage to the word lines WL1-WL8 which each select memory cells in each of the memory cell arrays MCA1-MCA8, each word line driver being connected to gate electrodes of memory cell transistors in each of the memory cell arrays MCA1-MCA8. Therefore, a plural number of word lines proportional to the number of the memory cells are provided in each of the memory cell arrays. The Vpp generator VPG generates the Vpp voltage and supplies it to each of word line drivers WD1-WD8, thereby simultaneously selecting the word lines WL1-WL8.
If a plurality of word lines are simultaneously activated and only a single Vpp generator is driven within the device, a resistance bridge as shown in the memory cell array MCA1 of FIG. 1 may undesirably occur. Such a resistance bridge is frequently formed when a metal becomes covered with dust or a contaminant before an etching process is executed, such that the, metal between two adjacent word lines is not etched during the execution of the etching process and the lines are shorted together.
FIG. 2 is a detailed circuit diagram showing the undesirable circuit characteristics that may occur when resistance bridge RB is formed between adjacent word lines. The Vpp generator VPG supplies the Vpp voltage to the word line driving circuit WDi and WDj, respectively. The word line driver WDi is comprised of a PMOS transistor Pi and an NMOS transistor Ni which are connected in serial between a Vpp voltage terminal and a ground voltage and connected commonly to a word line selection signal .phi.WSi at the gate electrodes thereof. The Vpp voltage driving the word line driver WDi is applied to the word line WLi. A cell transistor MCi and a cell capacitor CCi, which are connected in series between a bit line BLi and ground, serve as a memory cell for storing information, the cell transistor MCi hailing a gate electrode connected to the word line WLi. The word line driver WDj is comprised of a PMOS transistor Pj and an NMOS transistor Nj which are connected in series between the Vpp voltage terminal and a ground voltage and connected commonly to a word line selection signal .phi.WSj at the gate electrodes thereof. The Vpp voltage driving the word line driver WDj is applied to the word line WLj. A cell transistor MCj and a cell capacitor CCj, which are connected in series between a bit line BLj and the ground voltage, serve as a memory cell for storing information, the cell transistor MCj having a gate electrode connected to the word line WLj. Also, resistance bridge RB connects the word line WLi and WLj, which results in an undesirable abnormal connection therebetween.
During normal operation, the word line WLi is selected, the word line selection signal .phi.WSi is generated at a logic "low" state. Since the word line driving circuit WDi has an inverter structure, the PMOS transistor Pi is turned ON and the NMOS transistor Ni is turned OFF. As a result, the Vpp voltage generated in the Vpp generator VPG is supplied to the word line WLi. Sequentially, the cell trasistor MCi is mined ON and the information stored in the cell capacitor CCi is output to the bit line BLi. Since the information signal has a minute voltage, the cell transistor MCi is turned ON by the Vpp voltage and the information signal is output to the bit line BLi without any voltage drop. The voltage of the information signal is added to the voltage of precharged bit line BLi and the bit line BLi thus reaches a voltage that results from the addition of these voltages. Since the word line WLj adjacent to the word line WLi should not be selected, the word line selection signal .phi.WSj is generated at a logic "high" state. Because the word line driver WDj also has an inverter structure, the PMOS transistor Pj is turned OFF and the NMOS transistor Nj is turned ON. As a result, the Vpp voltage generated in the Vpp generator VPG is not normally supplied to the word line WLj. Thus, the cell trasistor MCj is turned OFF and the information signal stored in the cell capacitor CCj is not output to the bit line BLj and the bit line BLj maintains its precharged state.
When the word lines WLi and WLj are undesirably connected by the resistance bridge RB, the current generated by the Vpp voltage forms a current path flowing from the Vpp generator VPG through the following elements: the PMOS transistor Pi of the word line driver WDi, the word line WLi, the resistance bridge RB, the word line WLj, the NMOS transistor Nj of the word line driver WDj and the ground voltage. When such an undesirable current path is formed by the resistance bridge RB, the level of Vpp voltage falls. Therefore, if only a single Vpp generator VPG as shown in FIG. 1 is used, the voltages of all drivers using the Vpp voltage are accordingly lowered and normal operation cannot be performed in many instances. More particularly, since the resistance bridge RB causes the Vpp voltage to be lower than desired, a threshold voltage of the cell transistor MCi is added to the voltage of the information signal such that the information signal cannot be completely transmitted and thereby a malfunction is caused.
When the memory cell is accessed as shown in FIG. 1, eight word lines WL1 to WL8 are simultaneously selected. At this time, if a resistance bridge in the activated word line WL1, defects on all of the activated word lines WL2 to WL8 can exist. A conventional semiconductor memory device replaces defective word lines with redundant word lines. As a result, when only a single word line has a defect, the remaining normal word lines must be considered to be defective and thus must be replaced by redundant word lines, which does not allow efficient defect repair operation.